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iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 1/39 FEATURES o Latency-free sine-to-digital conversion to 400 angle steps o 500 kHz input frequency for interpolation factors of x1 and x2 (10 kHz for x100) o Flexible pin assignment due to signal path multiplexers o PGA inputs for differential and single-ended signals o Variable input resistance for current/voltage conversion o Signal conditioning for offset, amplitude and phase o Controlled 50 mA current source for LED or MR sensor supply o Fault-tolerant RS422 outputs with 50 mA sink/source drive current o Preselectable minimum phase distance for spike-proof counter stimulus o Zero signal conditioning and electronic index pulse generation o Signal and operation monitoring with configurable alarm output, output shutdown and error storage o I2 C multimaster interface for in-circuit calibration and parameters (EEPROM) o Adjustable overtemperature alarm and shutdown o Supply from 4.3 to 5.5 V, operation from -25(-40) to +100 C o Reverse polarity proof including the sub-system APPLICATIONS o Optical and magnetic position sensors o Angle encoders o Linear scales
PACKAGES
TSSOP20
BLOCK DIAGRAM
VDDS
VDD
GNDS
iC-MQ
SERIAL I2C INTERFACE CONFIGURATION REGISTER SINE-TO-DIGITAL CONVERSION PHI PGA INPUT LineCount Monitor Sin/Cos Monitor
REVERSE POLARITY PROTECTION
GND
SCL
MONITORING
C
PWRon
Tw Toff
ERR
SDA
SIGNAL PATH MUX
CALIBRATION
X1
I/V
x
CH0
DIGITAL DRIVER OUTPUT
PZ
X2
I/V
x x
CH1
SIGNAL LEVEL CONTROLLER
ZIN
NZ
X3
I/V
PB
X4
I/V
x x
CH2
x -
+
x
NB
+
ADJ
PA
X5
I/V
X6
I/U
x
x
NA
ACO
Copyright (c) 2006, 2010 iC-Haus
http://www.ichaus.com
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 2/39 DESCRIPTION Interpolator iC-MQ is a non-linear A/D converter which digitizes sine/cosine sensor signals using a count-safe tracking conversion principle with selectable resolution and hysteresis. The angle resolution per sine period can be set using SELRES; up to 400 angle steps are possible (see page 26). The angle position is output incrementally by differential RS422 drivers as an encoder quadrature signal with a zero pulse or, if selected, as a counter signal for devices compatible with 74HC191 or 74HC193. The zero pulse is generated electronically when an enable has been set by the X1/X2 inputs. This pulse can be configured extensively: both in its relative position to the input signal with regard to the logic gating with A and/or B and in its width from 90 to 360 (1/4 to 1 T). A preselectable minimum transition distance permits glitch-free output signals and prevents counting errors which in turn boosts the noise immunity of the position encoder. Programmable instrumentation amplifiers with selectable gain levels allow differential or single-ended, referenced input signals; via input X2 the external reference can be used as reference voltage for the offset correction. The modes of operation differentiate between high impedance (V modes) and low impedance (I modes). This adaptation of the iC to voltage or current signals enables MR sensor bridges or photosensors to be directly connected up to the device. The optical scanning of low resolution code discs is also supported by the reference function of input X2; these discs do not evaluate tracks differentially but in comparison with a reference photodiode. The integrated signal conditioning unit allows signal amplitudes and offset voltages to be calibrated accurately and also any phase error between the sine and cosine signals to be corrected. The channel for the zero signal can be configured separately. A control signal is generated from the conditioned signals which can track the transmitting LED of optical encoders via the integrated 50 mA driver stage (output ACO). If MR sensors are connected this driver stage can also track the power supply of the measuring bridges. By tracking the sensor energy supply any temperature and aging effects are compensated for, the input signals stabilized and the exact calibration of the input signals is maintained. This enables a constant accuracy of the interpolation circuit across the entire operating temperature range. When control limits are reached, these can be indicated at the maskable error pin ERR. Faults such as overdrive, wire breakage, short circuiting, dirt or aging, for example, are logged. iC-MQ includes extensive self-test and system diagnosis functions which check whether the sensor is working properly or not. For all error events the user can select whether the fault be displayed at error pin ERR or the outputs shutdown. At the same time errors can be stored in the EEPROM to enable failures to be diagnosed at a later stage. For encoder applications the line count of the code disc, the sensor signal regarding signal level and frequency and the operating temperature can be monitored, for example, the latter using an adjustable on-chip sensor. Display error pin ERR is bidirectional; a system fault recognized externally can be recorded and also registered in the error memory. iC-MQ is protected against reverse polarity and offers its monitored supply voltage to the external circuit, thus extending the protection to the system (for load currents to 20 mA). Reverse polarity protection also covers the short-circuit-proof line drivers so that an unintentional faulty wiring during initial operation is tolerated. On being activated the device configuration is loaded via the serial configuration interface from an external EEPROM and verified by a CRC. A microcontroller can also configure iC-MQ; the implemented interface is multimaster-competent and enables direct RAM access.
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 3/39 CONTENTS PACKAGES ABSOLUTE MAXIMUM RATINGS THERMAL DATA ELECTRICAL CHARACTERISTICS PROGRAMMING REGISTER MAP SERIAL CONFIGURATION INTERFACE Example of CRC Calculation Routine . . . . . EEPROM Selection . . . . . . . . . . . . . . I C Slave Mode (ENSL = 1) . . . . . . . . . . BIAS CURRENT SOURCE AND TEMPERATURE SENSOR CALIBRATION Bias Current . . . . . . . . . . . . . . . . . . Temperature Sensor . . . . . . . . . . . . . . OPERATING MODES Mode ABZ ................... ............... Mode 191/193 . . . . . . . . . . . . . . . . . Calibration 1, 2, 3 System Test TEST 6 . . . . . . . . . . . . . . . . . . . . . ..................
2
4 5 5 6 11 12 14 14 14 15
1. Photodiode array connected to current inputs, LED supply with constant current source . . . . . . . . . . . . . . 2. Encoder supplying 100 mVpp to voltage inputs . . . . . . . . . . . . . . . . . . . SIGNAL CONDITIONING CH0 Gain Settings CH0 . . . . . . . . . . . . . . . Offset Calibration CH0 . . . . . . . . . . . . . SIGNAL LEVEL CONTROL and SIGNAL MONITORING SINE-TO-DIGITAL CONVERSION OUTPUT SETTINGS AND ZERO SIGNAL Zero Signal Generation . . . . . . . . . Description Of CFGABZ Setup . . . . . Setup Example 1 . . . . . . . . . . . . . Setup Example 2 . . . . . . . . . . . . . Output Driver Configuration . . . . . . . Minimum Phase Distance . . . . . . . .
23 23 24 24 24
25 26 27 27 28 28 28 29 29 30 31 31 31 32 33 34 34 35 37 37 37 37
16 16 16 17 17 17 17 18 18 19 19 19 20 21 21 22 22 23
. . . . . .
. . . . . .
. . . . . .
ERROR MONITORING AND ALARM OUTPUT Error Protocol . . . . . . . . . . . . . . . . . . Line Count Error . . . . . . . . . . . . . . . . Temperature Monitoring . . . . . . . . . . . . REVERSE POLARITY PROTECTION TEST MODE Quick programming in the single master system . . . . . . . . . . . Quick programming in the multimaster system . . . . . . . . . . . . EXAMPLE APPLICATIONS APPLICATION HINTS In-circuit programming of the EEPROM . . . Absolute angle accuracy and edge jitter . . . Information on the demo board . . . . . . . .
INPUT CONFIGURATION Current Signals . . . . . . . . . . . . . . . . . Voltage Signals . . . . . . . . . . . . . . . . . SIGNAL PATH MULTIPLEXING SIGNAL CONDITIONING CH1, CH2 Gain Settings . . . . . . . . . . . . . . . . . . Offset Calibration CH1, CH2 . . . . . . . . . Phase Correction CH1 vs. CH2 . . . . . . . . Signal Conditioning Examples ........
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 4/39 PACKAGES PIN CONFIGURATION TSSOP20 PIN FUNCTIONS No. Name Function Signal Input 1 (Index +) Signal Input 2 (Index -) Signal Input 3 Signal Input 4 Switched Supply Output (reverse polarity proof, load to 20 mA max.) 6 GNDS Switched Ground (reverse polarity proof) 7 X5 Signal Input 5 8 X6 Signal Input 6 9 ACO Signal Level Controller, high-side current source output 10 SDA Serial Configuration Interface, data line 11 SCL Serial Configuration Interface, clock line 12 NB Incremental Output B13 PB Incremental Output B+ 14 NA Incremental Output A15 PA Incremental Output A+ 16 GND Ground 17 VDD +4.3...5.5 V Supply Voltage 18 NZ Incremental Output Z19 PZ Incremental Output Z+ 20 ERR Error Signal (In/Out) / Test Mode Trigger Input 1 2 3 4 5 X1 X2 X3 X4 VDDS
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 5/39 ABSOLUTE MAXIMUM RATINGS
These ratings do not imply operating conditions; functional operation is not guaranteed. Beyond these ratings device damage may occur. Item No. Symbol Parameter Voltage at VDD, PA, NA, PB, NB, PZ, NZ, SCL, SDA, ACO Voltage at ERR Pin-Pin Voltage Voltage at X1...X6, SCL, SDA Current in VDD Current in VDDS, GNDS Current in X1...X6, SCL, SDA, ERR Current in PA, NA, PB, NB, PZ, NZ Current in ACO ESD Susceptibility at all pins Permissible Power Dissipation Junction Temperature Storage Temperature -40 -40 HBM 100 pF discharged through 1.5 k -0.3 -20 -50 -20 -100 -100 Conditions Min. -6 -6 Max. 6 8 6 VDDS + 0.3 400 50 20 100 20 2 300 150 150 V V V V mA mA mA mA mA kV mW C C Unit
G001 V() G002 V() G003 V() G004 V() G005 I(VDD) G006 I() G007 I() G008 I() G009 I(ACO) G010 Vd() G011 Ptot G012 Tj G013 Ts
THERMAL DATA
Item No. T01 T02 Symbol Ta Rthja Parameter Operating Ambient Temperature Range (extended range to -40 C on request) Thermal Resistance Chip to Ambient Conditions Min. -25 80 Typ. Max. 100 C K/W Unit
All voltages are referenced to pin GNDS unless otherwise stated. All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative.
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 6/39 ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 4.3...5.5 V, Tj = -40 C...125 C, IBN calibrated to 200 A, unless otherwise stated Item No. Symbol Parameter Conditions Min. Permissible Supply Voltage Supply Current Permissible Load Current VDDS Clamp-Voltage hi at all pins Clamp-Voltage hi at Inputs SCL, SDA Clamp-Voltage hi at Inputs X1...X6 Clamp-Voltage lo at all pins Vc()hi = V() - V(VDD), I() = 1 mA Vc()hi = V() - V(VDD), I() = 4 mA I() = -4 mA 0.4 0.3 -1.2 0.75 0 -300 10 -10 16 1.1 1.6 2.2 3.2 1.35 2.25 20 1.6 2.3 3.2 4.6 0.15 RINi(0) = 0, BIASi = 1 RINi(0) = 0, BIASi = 0 RINi(3) = 0, GRi and GFi = 0x0 RINi(3) = 0, GRi and GFi = max. RINi(3) = 1, GRi and GFi = 0x0 RINi(3) = 1, GRi and GFi = max. 108 109 Gdiff G Relative Gain Ratio CH1 vs. CH2 GF2 = 0x10, GF1 = 0x0 GF2 = 0x10, GF1 = 0x7F Step Width Of Fine Gain Adjustment Integral Linearity Error of Gain Adjustment Recommended Differential Input Vin()diff = V(PCHx) - V(NCHx); RINi(3) = 0 Voltage RINi(3) = 1 Input Offset Voltage Offset Calibration Range referred to side of input referenced to the selected source (VOS0 resp. VOS12), mode Calibration 2; ORi = 00 ORi = 01 ORi = 10 ORi = 11 referenced to the selected source VOS0; OR0 = 0x0 referenced to the selected source VOS12; OR12 = 0x0 limited test coverage (guaranteed by design) CH1 vs. CH2 -5 20.2 for CH0 for CH1 for CH2 -1.06 1.5 2.5 2 100 0.5 25 39 255 1.06 1.015 1.06 1.06 % % 1.65 2.75 Load current I(VDDS) to 10 mA Load current I(VDDS) to 20 mA Tj = -40...125 C, no load Tj = 27 C, no load -20 4.3 4.5 12 0 11 1.5 1.2 -0.3 VDDS - 1.5 VDDS -10 300 10 24 2.1 3.0 4.2 6.0 Typ. Max. 5.5 5.5 25 V V mA mA mA V V V V V V A A A k k k k k %/K V V Unit
Total Device 001 V(VDD) 002 003 004 005 006 007 I(VDD) I(VDDS) Vcz()hi Vc()hi Vc()hi Vc()lo
Signal Conditioning, Inputs X1...X6 (CH1, CH2: i = 12, CH0: I = 0) 101 Vin()sig Permissible Input Voltage Range RINi() = 0x01 RINi() = 0x09 102 103 104 Iin()sig Iin() Rin() Permissible Input Current Range RINi(0) = 0; BIASi = 0 RINi(0) = 0; BIASi = 1 Input Current Input Resistance vs. VREFin RINi() = 0x01 Tj = 27 C; RINi(3:0) = 0x09 RINi(3:0) = 0x00 RINi(3:0) = 0x02 RINi(3:0) = 0x04 RINi(3:0) = 0x06
105 106 107
TC(Rin) VREFin() G0, G12
Temperature Coefficient of Rin Reference Voltages VREFin0, VREFin12 Selectable Gain Factors
110 111
INL(Gi) Vin()diff
10 40 25
500 2000
mVpp mVpp V
112 113
Vin()os VOScal
100 200 600 1200 3.2 0.79 5
%V() %V() %V() %V() % % LSB
114 115 116 117
OF0 OF12 INL(OFi) PHI12
CH0 Offset Calibration Step Width CH1/2 Offset Calibration Step Width Integral Linearity Error of Offset Calibration Phase Error Calibration Range
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 7/39 ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 4.3...5.5 V, Tj = -40 C...125 C, IBN calibrated to 200 A, unless otherwise stated Item No. 118 119 120 121 122 123 Symbol PHI12 Parameter Phase Error Calibration Step Width limited test coverage (guaranteed by design) -0.8 200 95 0.5 20 27 100 105 VDDS -2 30 Conditions Min. Typ. 0.63 0.8 Max. kHz % V k Unit
INL(PHI12) Integral Linearity Error of Phase Calibration fin() Vout(X2) Vin(X2) Rin(X2) Output Voltage at X2
Permissible Maximum Input Freq. analog signal path BIASEX = 10, I(X2) = 0, referenced to VREFin12
Permissible Input Voltage Range BIASEX = 11 at X2 Input Resistance at X2 BIASEX = 11, RIN0(3:0) = 0x01, RIN12(3:0) = 0x01 referenced to 360 input signal, ideal waveform, quasi static signals, adjusted signal conditioning, SELHYS = 0 referenced to output period T (see Fig. 1), ideal waveform, quasi static signals; at 4 edges per period at 100 edges per period at 384 edges per period at 400 edges per period see 201; VDD = const., Tj = const. Vs() = VDD - V(); SIK(1:0) = 00, I() = -1.2 mA SIK(1:0) = 01, I() = -4 mA SIK(1:0) = 10, I() = -20 mA SIK(1:0) = 11, I() = -50 mA SIK(1:0) = 00, I() = 1.2 mA SIK(1:0) = 01, I() = 4 mA SIK(1:0) = 10, I() = 20 mA SIK(1:0) = 11, I() = 50 mA V() = 0 V; SIK(1:0) = 00 SIK(1:0) = 01 SIK(1:0) = 10 SIK(1:0) = 11 V() = VDD; SIK(1:0) = 00 SIK(1:0) = 01 SIK(1:0) = 10 SIK(1:0) = 11 RL = 100 to GND; SSR(1:0) = 00 SSR(1:0) = 01 SSR(1:0) = 10 SSR(1:0) = 11 RL = 100 to VDD; SSR(1:0) = 00 SSR(1:0) = 01 SSR(1:0) = 10 SSR(1:0) = 11 TRIHL(1:0) = 11 (tristate) reversed supply voltage Op. modes Calibration 1, 2, 3 Op. modes Calibration 1, 2, 3
Sine-To-Digital Conversion 201 AAabs Absolute Angle Accuracy 0.9 1.8
202
AArel
Relative Angle Accuracy
<0.5 <2 0.1
10 10 10 10
% % % %
203
AAR
Repeatability
Line Driver Outputs PA, NA, PB, NB, PZ, NZ 501 Vs()hi Saturation Voltage hi
200 200 400 700 200 200 400 700 -4 -12 -60 -150 1.2 4 20 50 5 5 20 50 5 5 30 50 20 100 2.5 -3 110 800 50 4 3 -1.2 -4 -20 -50 4 12 60 150 20 40 140 350 20 40 140 350 100
mV mV mV mV mV mV mV mV mA mA mA mA mA mA mA mA ns ns ns ns ns ns ns ns A A k A ns ns %
502
Vs()lo
Saturation Voltage lo
503
Isc()hi
Short-Circuit Current hi
504
Isc()lo
Short-Circuit Current lo
505
tr()
Rise Time
506
tf()
Fall Time
507 508 509 510 511
Ilk()tri IIk()rev Rin()cal I()cal tclk()lo
Leakage Current Leakage Current Test Signal Source Impedance Permissible Test Signal Load
Clock Signal Low-Pulse Duration Op. mode Mode 191/193; MTD = 0x0 for CP, CPD, CPU MTD = 0x7 Duty Cycle referenced to output period T, see Fig. 1
512
tw()hi
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 8/39 ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 4.3...5.5 V, Tj = -40 C...125 C, IBN calibrated to 200 A, unless otherwise stated Item No. 513 514 Symbol tAB tMTD Parameter Phase Shift A vs. B Minimum Phase Distance Conditions Min. see Fig. 1 edge to edge, see Fig. 1; MTD = 0x0, IBN calibrated to 200 A MTD = 0x0, IBN calibrated to 220 A nominal values in Table 52 variation versus VDD = 5 V, Tj = 27 C due to VDD = 4.3...5.5 V or Tj = -40...125 C Vs() = VDD - V(); ADJ(8:0) = 0x11F, I(ACO) = -5 mA ADJ(8:0) = 0x13F, I(ACO) = -10 mA ADJ(8:0) = 0x15F, I(ACO) = -25 mA ADJ(8:0) = 0x17F, I(ACO) = -50 mA V() = 0 ... VDD - 1 V; ADJ(8:0) = 0x11F ADJ(8:0) = 0x13F ADJ(8:0) = 0x15F V() = 0 ... VDD - 1.2 V; ADJ(8:0) = 0x17F referenced to range ADJ(6:5) referenced to range ADJ(6:5) referenced to Vscq() referenced to Vscq() -10 -20 -50 -100 3 90 40 130 -18 +/- 2 Typ. 25 220 200 13.5 Max. % ns ns % % Unit
515 516
t()MTD t()MTD
Minimum Phase Distance Tolerance Minimum Phase Distance Variation
Signal Level Controller ACO 601 Vs()hi Saturation Voltage hi
1 1 1 1.2 -5 -10 -25 -50
V V V V mA mA mA mA %Isc %Isc %Vpp %Vpp
602
Isc()hi
Short-Circuit Current hi
603 604 605 606
It()min It()max Vt()min Vt()max
Control Range Monitoring 1: lower limit Control Range Monitoring 2: upper limit Signal Level Monitoring 1: lower limit Signal Level Monitoring 2: upper limit
Bias Current Source and Reference Voltages 801 IBN Bias Current Source
Calibration 1, I(NB) vs. VDDS; CFGIBN = 0x0 CFGIBN = 0xF IBN calibrated at T = 25 C
110 180 1.2 45 450 200 1.25 50 500 50 370 220 1.3 55 550
A A A V %VDDS mV %V05
802 803 804 805 901 902 903 B01 B02 B03
VBG VPAH V05 V025 VDDon VDDoff VDDhys Vs()lo Isc()lo Isc()
Internal Bandgap Reference Reference Voltage Reference Voltage V05 Reference Voltage V025 Turn-on Threshold VDD, PowerUp-Enable Turn-off Threshold VDD, PowerDown-Reset Hysteresis Saturation Voltage lo Short-Circuit Current lo Low-Side Current Source For Data Output Input Threshold Voltage hi Input Threshold Voltage lo Input Hysteresis Input-Pull-Up-Current Pull-Up-Voltage Test Mode Turn-on Threshold versus GND, I() = 4 mA versus GND, V(ERR) VDD versus GND, V(ERR) > VTMon L state Z state versus GND versus GND Vt()hys = Vt()hi - Vt()lo V() = 0...VDD - 1 V, EPU = 1 Vpu() = VDD - V(), I() = -5 A, EPU = 1 increasing voltage at ERR increasing voltage at VDD decreasing voltage at VDD
Power-Down-Reset 3.6 3.0 0.4 0.4 4 5 2 0 2 0.8 300 -400 500 -300 -200 0.4 VDD + 2 8 4.0 3.5 4.3 3.8 V V V V mA mA mA V V mV A V V
Error Signal Input/Output, Pin ERR
B04 B05 B06 B07 B08 B09
Vt()hi Vt()lo Vt()hys Ipu() Vpu() VTMon
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 9/39 ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 4.3...5.5 V, Tj = -40 C...125 C, IBN calibrated to 200 A, unless otherwise stated Item No. B10 B11 B12 B13 Symbol VTMoff VTMhys fclk() tp(ERR)in Parameter Test Mode Turn-off Threshold Conditions Min. decreasing voltage at ERR VDD + 0.5 0.15 120 480 0.3 160 640 10 200 800 Typ. Max. V V kHz kHz ms Unit
Test Mode Threshold Hysteresis VTMhys = VTMon - VTMoff Data Output Signal Frequency Process Delay for System Error Message at ERR ENFAST = 0 ENFAST = 1 upon power up (VDD > VDDon)
Reverse Polarity Protection and Supply Switches VDDS, GNDS C01 Vs() Saturation Voltage vs. VDD Vs(VDDS) = VDD - V(VDDS); I(VDDS) = -10...0 mA I(VDDS) = -20...-10 mA C02 Vs() Saturation Voltage vs. GND Vs(GNDS) = V(GNDS) - GND; I(GNDS) = 0...10 mA I(GNDS) = 10...20 mA C03 Irev(VDD) D01 Vs()lo D02 Isc()lo D03 Vt()hi D04 Vt()lo D05 Vt()hys D06 Ipu() D07 Vpu() D08 fclk() D09 tbusy()cfg Reversed Polarity Current Saturation Voltage lo Short-Circuit Current lo Input Threshold Voltage hi Input Threshold Voltage lo Input Hysteresis Input Pull-Up Current Pull-Up Voltage Clock Frequency at SCL Vt()hys = Vt()hi - Vt()lo V() = 0...VDDS - 1 V Vpu() = VDDS - V(), I() = -5 A ENFAST = 0 ENFAST = 1 60 240 80 320 0.8 300 -600 500 -300 V(VDD) = -5.5V...-4.3 V I = 4 mA 4 -1 Serial Configuration Interface SCL, SDA
150 250 150 200 0 400 75 2
mV mV mV mV mA mV mA V V mV
-60 0.4 100 400
A V kHz kHz
Duration of Startup Configuration IBN not calibated, EEPROM access without read failure, time to outputs operational; ENFAST = 0 ENFAST = 1 End Of I2C Communication; Time Until I2C Slave Is Enabled IBN not calibrated; V(SDA) = 0 V V(SCL) = 0 V or arbitration lost no EEPROM CRC ERROR SCL without clock signal: V(SCL) = constant; IBN not calibrated IBN calibrated to 200 A VTs() = VDDS - V(PA), Calibration 3, without Load; Tj = -40 C Tj = 27 C Tj = 100 C 25 64
36 24 4 indef. 45 95 80 80
48 34 12 135 285 240 120
ms ms ms ms ms ms s s
D10 tbusy()err
D11 tp()
Start Of Master Activity On I2C Protocol Error
Temperature Monitoring E01 VTs Temperature Sensor Voltage
740 620 460
770 650 520 -1.8
790 670 540
mV mV mV mV/K
E02 E03
TCs VTth
Temp. Co. Temperature Sensor Voltage Temperature Warning Activation Threshold VTth() = VDDS - V(NA), Tj = 27 C, Calibration 3, without Load; CFGTA(3:0) = 0x0 CFGTA(3:0) = 0xF
260 470
310 550 0.06
360 630
mV mV %/K C C C C
E04 E05 E06 E07
TCth Tw Thys T
Temp. Co. Temperature Warning Activation Threshold Warning Temperature CFGTA(3:0) = 0x0 CFGTA(3:0) = 0xF T = Toff - Tw 125 10 5
140 65 15 15
80 25 25
Warning Temperature Hysteresis 80 C < Tj < 125 C Relative Shutdown Temperature
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 10/39
tAB tMTD
B A
twhi AArel T AArel
Figure 1: Definition of relative angle error and minimum phase distance
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 11/39 PROGRAMMING Register Map, Overview . . . . . . . . . . . . . . . . . . . Page 12 Serial Configuration Interface . . . . . . . . . . . . . Page 14 ENFAST: I2 C Fast Mode Enable ENSL: I2 C Slave Mode Enable DEVID: Device ID of EEPROM providing the chip configuration data (e.g. 0x50) CHKSUM: CRC of chip configuration data (address range 0x00 to 0x2F) CHPREL: Chip Release END: Configuration Enable Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 16 CFGIBN: Bias Current CFGTA: Temperature Monitoring Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . Page 17 MODE: Operating Mode Input Configuration and Signal Path Multiplexer . . . . . . . . . . . . . . . Page 19 INMODE: Diff./Single-Ended Input Mode RIN12: I/V Mode and Input Resistance CH1, CH2 BIAS12: Reference Voltage CH1, CH2 RIN0: I/V Mode and Input Resistance CH0 BIAS0: Reference Voltage CH0 BIASEX: Input Reference Selection INVZ: Index Signal Inversion MUXIN: Input-To-Channel Assignment: X3...X6 to CH1, CH2 Signal Conditioning CH1, CH2 (X3...X6) . . . Page 21 GR12: Gain Range CH1, CH2 (coarse) GF1: Gain Factor CH1 (fine) GF2: Gain Factor CH2 (fine) VOS12: Offset Reference Source CH1, CH2 VDC1: Intermediate Voltage CH1 VDC2: Intermediate Voltage CH2 OR1: Offset Range CH1 (coarse) OF1: Offset Factor CH1 (fine) OR2: Offset Range CH2 (coarse) OF2: Offset Factor CH2 (fine) PH12: Phase Correction CH1 vs. CH2 Signal Conditioning CH0 (X1, X2) . . . . . . . . . Page 24 GR0: Gain Range CH0 (coarse) GF0: Gain Factor CH0 (fine) VOS0: Offset Reference Source CH0 OR0: Offset Range CH0 (coarse) OF0: Offset Factor CH0 (fine) Signal Level Controller . . . . . . . . . . . . . . . . . . . . Page 25 ADJ: Setup of ACO Output Function Sine-To-Digital Conversion . . . . . . . . . . . . . . . . Page 26 SELRES: Resolution SELHYS: Hysteresis Quadrature Output Logic . . . . . . . . . . . . . . . . . . Page 27 CFGABZ: Output Logic CFGZPOS: Zero Signal Positioning ENZFF: Zero Signal Synchronisation Quadrature Output Settings . . . . . . . . . . . . . . . Page 29 MTD: Minimum Phase Distance SIK: Driver Short-Circuit Current SSR: Driver Slew Rate TRIHL: Driver Mode Error Monitoring and Alarm Output . . . . . . . Page 30 EMTD: Minimal Alarm Indication Time EPH: Alarm Input/Output Logic EPU: Alarm Output Pull-Up Enable EMASKA: Error Mask For Alarm Indication (pin ERR) EMASKE: Error Mask For Protocol (EEPROM) EMASKO: Error Mask For Driver Shutdown PDMODE: Driver Activation After Cycling Power LINECNT: Line Count (Pulses) Between 2 Zero Pulses ERR1: Error Protocol: First Error ERR2: Error Protocol: Last Error ERR3: Error Protocol: History Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 33 EMODE: Test Mode EMODE2: Register And Address Selection For Test Mode
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 12/39 REGISTER MAP
Register Map Adr
0x00
Bit 7 ENFAST
Bit 6
Bit 5
Bit 4
Bit 3 DEVID(6:0)
Bit 2
Bit 1
Bit 0
Serial Configuration Interface Calibration
0x01
CFGIBN(3:0)
END 1 0 ENZFF
CFGTA(3:0) MODE(3:0)
INVZ INMODE
Operating Mode
0x02
Input Configuration
0x03 0 0 0 0
MUXIN(1:0) GR12(2:0)
Signalkonditionierung CH1, CH2
0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0 0 VDC1(0) 0 0 0
GF2(4:0) GF1(3:0)
0 0 0
0 0
0
0
0
GF1(6:4) VDC1(5:1)
0
OR1(0) OF1(3:0)
VDC2(5:0)
0 0 0
OR1(1) 0
OR2(1:0) OF2(6:0)
0 0 1 0 1 0
OF1(7:4)
0 OF2(7)
PH12(2:0) BIASEX(1:0)
1 BIAS12
VOS12(1:0)
0 1 0 0
PH12(5:3) RIN12(3:0)
0 0
Signal Level Controller
0x0F 0x10 ADJ(0) --
ADJ(8:1) GF0(4:0) OF0(5:0) VOS0(1:0) EMASKA(7:0) EMTD(2:0) EMASKO(7:0)
ENSL
Signal Conditioning CH0
0x11 0x12 0x13 0 BIAS0
GR0(2:0) OR0(1:0) RIN0(3:0)
Error Monitoring and Alarm Output
0x14 0x15 0x16 0x17 0x18 EMODE2
EMODE(1:0) EMASKE(3:0)
PDMODE
EPH EPU
EMASKA(9:8) EMASKO(9:8)
EMASKE(9:4) CFGABZ(7:0) CFGZPOS(7:0) SELRES(7:0) SELRES(14:8)
Zero Signal Output
0x19 0x1A
Sine-To-Digital Conversion, Minimum Phase Distance
0x1B 0x1C 0x1D --
MTD(3:0)
-- --
SELHYS(3:0) SIK(1:0) SSR(1:0) TRIHL(1:0)
Output Driver Settings
0x1E
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 13/39 Register Map Adr
0x1F 0x20 0 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Line Counter
LINECNT(7:0) LINECNT(13:8)
0 0 1 0 0 0
Reserved
0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0 0
0x00 (recommended programming) 0x00 (recommended programming) free for OEM data free for OEM data free for OEM data free for OEM data free for OEM data free for OEM data free for OEM data free for OEM data free for OEM data free for OEM data free for OEM data CHKSUM(7:0) of EEPROM data [CHPREL(7:0), refer to Table 7]
Check Sum
0x2F
Error Register
0x30 0x31 0x32 0x33 Notes -- --
ERR1(7:0) ERR2(5:0) ERR3(3:0) ERR3(9:4)
The device RAM initially contains random data following power-on.
ERR1(9:8) ERR2(9:6)
Table 4: Register layout (EEPROM)
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 14/39 SERIAL CONFIGURATION INTERFACE The serial configuration interface consists of the two pins SCL and SDA and enables read and write access to an EEPROM with an I2 C interface. The readout clock rate can be selected using ENFAST.
ENFAST Code 0 1 Notes Adr 0x00, bit 7 Function Regular clock rate, f(SCL) approx. 80 kHz High clock rate, f(SCL) approx. 320 kHz For in-circuit programming bus lines SCL and SDA require pull-up resistors. For line capacitances to 170 pF, adequate values are: 4.7 k with clock frequency 80 kHz 2 k with clock frequency 320 kHz The pull-up resistors may not be less than 1.5 k. To separate the signals a ground line between SCL and SDA is recommended. iC-MQ requires a supply voltage during EEPROM programming (5 V to VDD). ENSL Code 0 1 Adr 0x17, bit 3 Function Normal operation I2 C Slave Mode Enable (Device ID 0x55)
Table 6: Config. Interface Mode The device ID for the EEPROM can be entered in register DEVID(6:0) (address 0x00), from which iC-MQ will take its configuration after exiting test mode (see page 33). The DEVID stored therein is then accepted. Example of CRC Calculation Routine
unsigned char ucDataStream = 0 ; i n t iCRCPoly = 0x11D ; unsigned char ucCRC=0; int i = 0; ucCRC = 1 ; / / s t a r t v a l u e ! ! ! f o r ( iReg = 0 ; iReg <47; iReg ++) { ucDataStream = ucGetValue ( iReg ) ; f o r ( i =0; i <=7; i ++) { i f ( ( ucCRC & 0x80 ) ! = ( ucDataStream & 0x80 ) ) ucCRC = (ucCRC << 1 ) ^ iCRCPoly ; else ucCRC = (ucCRC << 1 ) ; ucDataStream = ucDataStream << 1 ; } }
Table 5: Clock Frequency Configuration Interface
Once the supply has been switched on the iC-MQ outputs are high impedance (tristate*) until a valid configuration is read out from the EEPROM using device ID 0x50. Bit errors in the 0x00 to 0x2F memory section are pinpointed by the CRC deposited in register CHKSUM(7:0) (address 0x2F in the EEPROM; the CRC polynomial used is "'1 0001 1101"' with a start value of "1"). Should the read configuration data not be confirmed by the CRC, the readin process is repeated. If no valid configuration data is available after a fourth readin, iCMQ terminates EEPROM access and switches to I2 C slave mode. This switch takes place after 150 ms at the latest (see Electrical Characteristics, D11), for example when no EEPROM is connected. For devices loading a valid configuration from the EEPROM register bit ENSL decides whether the I2 C slave function is enabled or not.
EEPROM Selection The following minimal requirements must be fulfilled: * Operation from 3.3 to 5 V, I2 C interface * At least 512 bits, 64x8 (address range used is 0x00 to 0x3F) * Support of Page Write with Pages of at least 4 bytes. Errors can otherwise not be saved to the EEPROM (EMASKE = 0x0). * Device ID 0x50 "1010 000", no occupation of 0x55 (A2...A0 = 0). iC-MQ can otherwise not be accessed via 0x55 in I2 C slave mode. Recommended M24C01W device: Atmel AT24C01B, ST
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 15/39 I2 C Slave Mode (ENSL = 1) In this mode iC-MQ behaves like an I2 C slave with the device ID 0x55 and the configuration interface permits write and read accesses to iC-MQ's internal registers. For chip release verification purposes an identification value is stored under ROM address 0x2F; a write access to this address is not permitted.
CHPREL Code 0x00 0x04 0x08 0x09 Adr 0x2F, bit 7:0 (ROM) Chip Release Not available iC-MQ 3 iC-MQ X iC-MQ X1 Register RAM Addr 0x00-0x21 0x22-0x2A 0x2B-0x2E 0x2F 0x30-0x33 0x34-0x3A 0x3B-0x3E 0x3F 0x40-0x43 Read access via I2 C slave mode (ENSL = 1) Content Configuration data (see EEPROM addresses 0x00-0x21) Not available Configuration data (see EEPROM addresses 0x2B-0x2E) Chip release CHPREL(7:0) Configuration data (see EEPROM addresses 0x30-0x33) Not available Configuration data (see EEPROM addresses 0x2B-0x2E) Chip release CHPREL(7:0) Current error memory (only active when enabled by EMASKE; messages will be transferred to EEPROM Addresses 0x30-0x33) Not available
Table 7: Chip Release
END Code 0 1 Adr 0x02, bit 7 Function Sin/D converter and line driver disabled (RAM configuration data invalid) Restart of Sin/D conversion, line driver active (RAM configuration data valid)
0x44-0x7F
Table 9: RAM Read Access
Register RAM Addr 0x00 0x01 0x02 Write access via I2 C slave mode (ENSL = 1) Access and conditions Changes possible, no restrictions Changes possible (wrong entries for CFGIBN can limit functions) Changes to bits 6:0 are permitted only when Sin/D conversion is halted (END = 0, ie. bit 7); Restarting Sin/D conversion by changing END (bit 7) is permitted only with no changes of operating mode (bits 6:0 remain as set) Changes possible, no restrictions Changes to bits 7:4 and 2:0 are permitted (ENSL, bit 3 must be kept 1) Changes possible, no restrictions Changes possible when Sin/D conversion is halted (END = 0) Changes possible, no restrictions No write access permitted No write access permitted Not available
Table 8: Configuration Enable
0x03-0x16 0x17 0x18 0x19-0x21 0x2B-0x2E 0x2F-0x3F 0x40-0x43 0x44-0x7F
Table 10: RAM Write Access Notes: The converter function should be halted by END = 0 for the deletion of errors saved in the EEPROM (Dev-ID 0x50, Addresses 0x30-0x33). Otherwise active errors could be transferred to the EEPROM again (from addresses 0x40-0x43 if enabled by EMASKE).
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 16/39 BIAS CURRENT SOURCE AND TEMPERATURE SENSOR CALIBRATION Bias Current The calibration of the bias current source in operation mode Calibration 1 (see Table 13) is prerequisite for adherence to the given electrical characteristics and also instrumental in the determination of the chip timing (e.g. clock frequency at SCL). For setup purposes the IBN bias current is measured using a 10 k resistor by pin VDDS connected to pin NC. The setpoint is 200 A which is equivalent to a voltage drop of 2 V.
CFGIBN Code k 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Adr 0x01, bit 7:4 31 IBN 39-k 79 % 81 % 84 % 86 % 88 % 91 % 94 % 97 %
Example: VTs(T1 ) is ca. 650 mV, measured from VDDS versus PA, with T1 = 25 C; The necessary reference voltage VTth(T1 ) is then calculated. The required warning temperature T2 , temperature coefficients TCs and TCth (see Electrical Characteristics, Section E) and measurement value VTs(T1 ) are entered into this calculation:
Code k 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF
IBN 100 % 103 % 107 % 111 % 115 % 119 % 124 % 129 %
31 39-k
VTth(T1 ) =
VTs(T1 ) + TCs * (T2 - T1 ) 1 + TCth * (T2 - T1 )
Example: For T2 = T1 + 100 K VTth(T1 ) must be programmed to 443 mV. Reference voltage VTth(T1 ) is provided for a high impedance measurement (10 M) at output pin NA (measurement versus VDDS) and must be set by programming CFGTA(3:0) to the calculated value. Example: Altering VTth(T1 ) from 310 mV (measured with CFGTA(3:0)= 0x0) to 443 mV is equivalent to 143 %, the closest value for CFGTA is 0x9;
CFGTA Code k 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Notes Adr 0x01, bit 3:0 VTth 65+3k 65 100 % 105 % 110 % 115 % 120 % 125 % 130 % 135 %
Table 11: Calibration of Bias Current Temperature Sensor The temperature monitoring is calibrated in operating mode Calibration 3. To set the required warning temperature T2 the temperature sensor voltage VTs at which the warning message is generated is first determined. To this end a voltage ramp from VDDS towards GNDS is applied to pin PA until pin ERR displays the warning message. The following settings are required here: EMASKA = 0x20, EMTD = 0x00 and EPH = 0x00. The signal at ERR first switches from tristate to low (on reaching the warning threshold VTs) and then from low to tristate (on overshooting the internal hysteresis which is not relevant to calibration). To avoid confusion a clear change of state (from low to high) must be generated with the help of an external pull-up resistor at pin ERR.
Code k 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF
VTth 140 % 145 % 150 % 155 % 160 % 165 % 170 % 175 %
65+3k 65
With CFGTA = 0xF Toff is 80 C typ., with CFGTA = 0x0 Toff is 155 C typ.
Table 12: Calibration of Temperature Monitoring
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 17/39 OPERATING MODES iC-MQ has various modes of operation, for which the functions of outputs PA, NA, PB, NB, PZ, NZ and ERR are altered. Two operating modes can be selected for the output of the angle position in normal operation. Mode 191/193 provides control signals for devices compatible with 74HC191 or 74HC193, whereas in Mode ABZ the angle position is output incrementally as an enMODE(3:0) Code 0x00 0x0F 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E Operating Mode Mode ABZ Mode 191/193 Calibration 1 Calibration 2 Test 3* Test 4* Test 5* Test 6* Calibration 3 Lo-Signal Hi-Signal Test 10* System Test* Test 12* -- IDDQ Test* Hints Addr. 0x02; bit 3:0 PA A CPD TANAZ(2) PCH1 VPAH PS_out PSIN PCH1I VTs NA not(A) CPU VREFIZ NCH1 VPD NS_out NSIN NCH1I VTth PB B CP VREFISC PCH2 -- PC_out PCOS PCH2I -- NB not(B) nU/D IBN NCH2 CGUCK NC_out NCOS NCH2I -- PZ Z MR PCH0 VDC1 IPF PZO PZO VDC1 VTTFE NZ not(Z) nPL NCH0 VDC2 V05 NZO NZO VDC2 VTTSE IERR IERR IERR res. ERR ERR ERR ERR IERR
coder quadrature signal with a zero pulse. Only in these modes are the line drivers and the reverse polarity protection feature active. In order to condition the input signals and to calibrate and test iC-MQ Calibration and Test modes are available. Digital and analog test signals are provided; the latter must always be measured at high load impedance.
All outputs and SCL, SDA, ERR to low level All outputs to high level TP A4 A -- CLK6 A8 not(A) -- CLK1 B4 B -- CLK3/8 B8 not(B) -- ZIn ZIn Z -- CLK4 TP1 not(Z) -- ERR ERR --
All PU/PD resistors, oscillator and analog supply voltage deactivated. *) Test function for iC-Haus device test only.
Table 13: Operating Modes Mode ABZ In Mode ABZ A/B signals are generated and output via PA, NA, PB and NB. A freely configurable zero signal is simultaneously provided at pins PZ and NZ. The differential RS422 line drivers are active; an Nx pin constantly supplies a complementary signal which is the inversion of pin Px.
Mode 191/193 Pin Signal PA NA PB NB PZ CPD CPU CP nU/D MR Description Clock Down Pulse Clock Up Pulse Clock Pulse Count Direction (0: up, 1: down) Asynch. Master Reset (active high) Signal is '1' if index position is reached, otherwise '0'. Asynch. Parallel Load Input (active low) / Reset (active low) Signal is '0' if index position is reached, otherwise '1'.
NZ
nPL
Mode 191/193 In Mode 191/193 the output pins provide control signals for counter devices compatible with 74HC191 or 74HC193 according to the following table. The driving capability (SIK) and the slew rate (SSR) of the output drivers must be selected so that the clock pulses can be output with a low pulse of typically 50 ns (see Electrical Characteristics, 511).
Table 14: Operating mode for counter devices compatible with 74HC191 or 74HC193.
Calibration 1, 2, 3 These modes are used to condition the input signals and calibrate iC-MQ. In mode Calibration 1 the user can measure the IBN bias current and the zero chan-
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 18/39 nel analog signals are available following signal conditioning (PCH0 and NCH0). In mode Calibration 2 the conditioned sine and cosine signals are output (PCH1, NCH1, PCH2 and NCH2). In addition intermediate potential VDC1 is provided for compensating circuit CH1, as is intermediate potential VDC2 for CH2 (for a description of the calibration process, see page 21). In mode Calibration 3 the internal temperature monitoring signals are provided. Calibration of the bias current source and temperature monitoring is described on page 16 and calibration of the zero channel on page 24. TEST 6 The input voltages at pins X3 to X6 can be checked in mode Test 6. The following settings are required here: * GF1 = 0x0 * GF2 = 0x0 * Byte 0x05, bit 3:0 = '0000' * Byte 0x0F, bit 3 = '1' * Byte 0x0F, bit 4 = '0' System Test This mode enables the signal conditioning to be adjusted using comparated sine and cosine signals. To
PZ NZ ZIn TP1
this end at a resolution of 8 the interpolator generates a switchpoint every 45 degrees. The objective of the calibration procedure is a pulse duty cycle of exactly 50% respectively for A4 , B4 und A8 , B8 . The following settings are required for mode System Test:
* MODE = 0x0B * SELRES = 0x1B0 * SELHYS = 0xF * CFGABZ(7:4) = '0000'
System Test Pin Signal PA NA PB NB A4 A8 B4 B8
Description Offset CH1 Phase deviation from 90 between CH1 and CH2 Offset CH2 Amplitude deviation between CH1 and CH2 Digital zero signal, unmasked Verification of line count (pulses) between two zero pulses Low signal: verification running (state after power on reset) High signal: verification finished An error messaging at ERR is valid after the second zero signal (enable required).
Table 15: Digital Calibration Signals
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 19/39 INPUT CONFIGURATION All input stages are configured as instrumentation amplifiers and thus directly suitable for differential input signals. Referenced input signals can be processed; input X2 can be configured as a reference input. Both current and voltage signals can be processed, selected using RIN12 and RIN0.
INMODE Code 0 1 Note Adr 0x03, bit 2 Function Differential input signals Single-ended input signals * * Input X2 is reference for all inputs.
Figure 2: Signal Conditioning
Table 16: Input Signal Mode Current Signals In I Mode an input resistor Rin() becomes active at each input pin, converting the current signal into a voltage signal. Input resistance Rin() consists of a pad wiring resistor and resistor Rui() which is linked to the adjustable bias voltage source VREFin(). BIASEX must be set to '00'. The table besides shows the possible selections, with Rin() giving the typical resulting input resistance (see Electrical Characteristics for tolerances). The input resistor should be set in such a way that intermediate potentials VDC1 and VDC2 lie between 125 mV and 250 mV (verifiable in mode Calibration 2). Voltage Signals In V mode an optional voltage divider can be selected which reduces unacceptably large input amplitudes to ca. 25 %. The circuitry is equivalent to the resistor chain in I mode; the pad wiring resistor is considerably larger here, however. For sensors whose offset calibration is to be proportional to an external DC voltage source the reference source can be selected using BIASEX; for all other sensors BIASEX should be set to '00'.
RIN12 RIN0 Code -000 -010 -100 -110 1--1 0--1 Adr 0x0E, bit 3:0 Adr 0x13, bit 3:0 Nominal Rin() 1.7 k 2.5 k 3.5 k 4.9 k 20 k high impedance Internal Rui() 1.6 k 2.3 k 3.2 k 4.6 k 5 k 1 M I/V Mode current input current input current input current input voltage input voltage input
Table 17: I/V Mode and Input Resistance
BIAS12 BIAS0 Code 0 1 Note Adr 0x0E, bit 6 Adr 0x13, bit 6 VREFin() Type of sensor 2.5 V 1.5 V Lowside sink current (I Mode) Highside current source (I Mode)
Not valid with BIASEX=11.
Table 18: Reference Voltage
BIASEX Code 00* 10 11 Adr 0x0D, bit 7:6 VREFin() 1.5 / 2.5 V (internal) 1.5 / 2.5 V (internal) external Signal at X2 Neg. Zero Signal (Index -), input Ref. Voltage VREFin12, output Voltage at X2 supplies VREFin
Table 19: Input Reference Selection
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 20/39 SIGNAL PATH MULTIPLEXING
MUX_IN
X1
Calibration
MUX_OUT
X2
VREFin0 MUXIN(0) 01 MUXIN(1)
PCH0i NCH0i
+
PCH0o 0 NCH0o
INVZ 1
PZO
+
X3
+
NZO
PC_out NC_out
ZIN
X4
PCH2i NCH2i
PCH2o NCH2o
X5
0
1 PCH1i
+
PCH1o NCH1o VDC1 VDC2
PS_out NS_out VDC1 VDC2
X6
MUXIN(1) 0 1
INMODE
NCH1i
-
VREFin12
Figure 3: Principle Of Multiplexer Function The signals for index channel CH0 are connected up to pins X1 and X2. Pins X3 to X6 are allocated to internal channels CH1 and CH2 via MUXIN. INMODE can be activated for referenced input signals; this then selects X2 as the reference signal input. For output purposes INVZ allows the index signal phase to be inverted for channel CH0.
MUXIN Code 00 01 10 11 Adr 0x03, bit 1:0 PCH1i NCH1i X4 not permitted X4 X4 X5 X3 X3 X5 X6 X6 X6 MUXIN Code 00 01 10 11 Adr 0x03, bit 1:0 PCH1i NCH1i X4 not permitted not permitted X4 X2 X5 X2 X2
PCH2i X3
NCH2i X2
Table 21: Input Multiplexer for INMODE = 1
PCH2i X3 NCH2i X5 INVZ Code 0 1 Adr 0x03, bit 3 PZO PCH0o NCH0o NZO NCH0o PCH0o
Table 20: Input Multiplexer for INMODE = 0
Table 22: Index Signal Inversion
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 21/39 SIGNAL CONDITIONING CH1, CH2 The analog voltage signals necessary for the calibration of the sine signals can be measured in operation mode Calibration 2. Alternatively, characteristic digital test signals are also available for offset, amplitude and phase errors in operating mode System Test. Gain Settings The gain is set in four steps: 1. The sensor supply controller is shut down and the constant current source for the ACO output set to a suitable output current (register ADJ; current value close to the later operating point). 2. The coarse gain is selected so that differential signal amplitudes of ca. 1 Vpp are produced internally (signal Px versus Nx, see Figure). 3. Using fine gain factor GF2 the CH2 signal amplitude is then adjusted to 1 Vpp. 4. The CH1 signal amplitude can then be adjusted to the CH2 signal amplitude via fine gain factor GF1. This results in a total gain of GR12 * GFi for differential input signals.
GR12 Code 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Adr 0x04, bit 2:0 Range RIN12=0x9 0.5 1.0 1.3 1.7 2.2 2.6 3.3 4.0
Range RIN12=0x9 2.0 4.1 5.3 6.7 8.7 10.5 13.2 16.0
Table 23: Gain Range CH1, CH2
GF2 Code 0x00 0x01 ... 0x1F Adr 0x04, bit 7:3 Factor 1.00 1.06 6.25 6.25
GF 2 31
Table 24: Fine Gain Factor CH2
GF1 Code 0x00 0x01 ... 0x7F Adr 0x06, bit 2:0, Adr 0x05, bit 7:4 Factor 1.0 1.015 6.25 124 6.53
GF 1
Table 25: Fine Gain Factor CH1
Px
VPx Nx VNx GND
R0
VPNx
Figure 4: Definition of 1 Vpp signal. Termination R0 must be high-ohmic during all Test and Calibration modes.
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 22/39 Offset Calibration CH1, CH2 In order to calibrate the offset the reference source must first be selected using VOS12. Two fixed voltages and two dependent sources are available for this purpose. The fixed voltage sources should be selected for external sensors which provide stable, self-regulating signals. So that photosensors can be operated in optical encoders iC-MQ tracks changes in offset voltages via the signal-dependent source VDC when used in conjunction with the controlled sensor current source for LED supply (pin ACO). The VDC potential automatically tracks higher DC photocurrents. To this end intermediate potentials VDC1 and VDC2 must be adjusted to a minimal AC ripple using the selectable k factor (this calibration must be repeated when the gain setting is altered). The ideal DC voltage level of 0.125 V to 0.25 V is selected via input resistor Rui(). The feedback of pin voltage V(ACO) fulfills the same task as source VDC when MR bridge sensors are supplied by the controlled sensor current source. In this instance the VDC sources do not need adjusting.
VOS12 Code 0x0 0x1 0x2 0x3 Adr 0x0E, bit 5:4 Source 0.05 * V(ACO) 0.5 V 0.25 V VDC (VDC1 for CH1, VDC2 for CH2)
The offset calibration range for CH1 and CH2 is dependent on the selected VOS12 source and is set using OR1 and OR2. Both sine and cosine signals are then calibrated using factors OF1 and OF2. The calibration target is reached when the DC fraction of the differential signals PCHi versus NCHi is zero.
OR1 OR2 Code 0x0 0x1 0x2 0x3 Adr 0x09, bit 0; Adr 0x08, bit 7 Adr 0x0A, bit 5:4 Range x1 x2 x6 x12
Table 28: Offset Range CH1, CH2
OF1 OF2 Code 0x00 0x01 ... 0x7F Adr 0xA, bit 3:0; Adr 0x9, bit 7:4 Adr 0xC, bit 0; Adr 0xB, bit 7:1 Factor Code 0 0.0079 0.0079 * OFi 1 0x80 0x81 ... 0xFF Factor 0 -0.0079 -0.0079 * OFi -1
Table 29: Offset Factors CH1, CH2 Phase Correction CH1 vs. CH2 The phase shift between CH1 and CH2 can be adjusted using parameter PH12. Following phase calibration other calibration parameters may have to be adjusted again (those as amplitude compensation, intermediate potentials and offset voltages).
PH12 Code 0x00 0x01 ... 0x1F Adr 0xD, bit 2:0; Adr 0xC, bit 7:5 Correction angle Code Correction angle +0 +0.65 +0.65 * PH12 +20.2 0x20 0x21 ... 0x3F -0 -0.65 -0.65 * PH12 -20.2
Table 26: Offset Reference Source CH1, CH2
VDC1 VDC2 Code 0x00 0x01 ... 0x3F Adr 0x07, bit 4:0; Adr 0x06, bit 7 Adr 0x08, bit 6:1 VDC = k * VPi + (1 - k) * VNi k k k k = = = = 0.33 0.335 0.33 + VDCi * 0.0052 0.66
Table 27: Intermediate Voltages CH1, CH2
Table 30: Phase Correction CH1 vs. CH2
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 23/39 Signal Conditioning Examples
1. Photodiode array connected to current inputs, LED supply with constant current source
Step 1.
Operating Mode
Calibration and Signal Presets VOS12= 0x3, GF1= 0x40, VDC1= 0x20, OF1= 0x0, GF2= 0x10, VDC2= 0x20, OF2= 0x0 Example: LED current approx. 6.25 mA ADJ(8)= 1 (constant current source), ADJ(6:5)= 11 (range 50 mA), ADJ(4:0)= 0x04 (value 12.5)
2.
Calibration 2
Calibration of Channel 1: Parameter GR12: Adjust diff. signal at PA vs. NA to approx. 1 Vpp amplitude Parameter GF1: Adjust diff. signal at PA vs. NA to exactly 1 Vpp amplitude Parameter VDC1: Minimization of VDC1 AC fraction at output PZ (ripple < 10 mVpeak) Parameter OR1, OF1: Calibration of DC fraction to zero for diff. signal PA vs. NA (< 5 mVdc) Calibration of Channel 2: Parameter GF2: Adjust diff. signal at PB vs. NB to exactly 1 Vpp amplitude Parameter VDC2: Minimization of VDC2 AC fraction at ouput NZ (ripple < 10 mVpeak) Parameter OR2, OF2: Calibration of DC fraction to zero for diff. signal PB vs. NB (< 5 mVdc) 1. Iteration, Calibration of Channel 1 vs. Channel 2: Parameter OF1: Adjust duty ratio of A4 at PA to 50 % Parameter OF2: Adjust duty ratio of B4 at PB to 50 % Parameter PH12: Adjust duty ratio of A8 at NA to 50 % Parameter GF1: Adjust duty ratio of B8 at NB to 50 % Repeated Adjustment of Intermediate Voltages, VDC1 and VDC2: Parameter VDC1: Minimization of VDC1 AC fraction at ouput PZ Parameter VDC2: Minimization of VDC2 AC fraction at ouput NZ 2. Iteration, Calibration of Channel 1 vs. Channel 2: Parameter OF1: Adjust duty ratio of A4 at PA to 50 % Parameter OF2: Adjust duty ratio of B4 at PB to 50 % Parameter PH12: Adjust duty ratio of A8 at NA to 50 % Parameter GF1: Adjust duty ratio of B8 at NB to 50 %
3.
Calibration 2
4.
System Test
5.
Calibration 2
6.
System Test
Table 31: Conditioning example 1 2. Encoder supplying 100 mVpp to voltage inputs
Step 1. 2.
Operating Mode
Calibration and Signal Presets VOS12= 0x1, GF1= 0x40, OF1= 0x0, GF2= 0x10, OF2= 0x0
Calibration 2
Calibration of Channel 1: Parameter GR12: Adjust diff. signal at PA vs. NA to approx. 1 Vpp amplitude Parameter GF1: Adjust diff. signal at PA vs. NA to exactly 1 Vpp amplitude Parameter OR1, OF1: Calibration of DC fraction to zero for diff. signal PA vs. NA (< 5 mVdc) Calibration of Channel 2: Parameter GF2: Adjust diff. signal at PB vs. NB to exactly 1 Vpp amplitude Parameter OR2, OF2: Calibration of DC fraction to zero for diff. signal PB vs. NB (< 5 mVdc) Calibration of Channel 1 vs. Channel 2: Parameter OF1: Adjust duty ratio of A4 at PA to 50 % Parameter OF2: Adjust duty ratio of B4 at PB to 50 % Parameter PH12: Adjust duty ratio of A8 at NA to 50 % Parameter GF1: Adjust duty ratio of B8 at NB to 50 %
3.
Calibration 2
4.
System Test
Table 32: Conditioning example 2
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 24/39 SIGNAL CONDITIONING CH0 The voltage signals needed to calibrate the zero channel are available in mode Calibration 1. The relative phase position of the ungated zero signal Zin compared to A and B can be determined in mode System Test. Gain Settings CH0 Parallel to the conditioning process for the CH1 and CH2 signals the CH0 gain is also set in the following steps: 1. The sensor supply controller is shut down and the constant current source for the ACO output set to the same output current as in the calibration of CH1 and CH2 (register ADJ; current value close to the later operating point). 2. The coarse gain is selected so that a differential signal amplitude of ca. 1 Vpp is produced internally (signal PCHi versus NCHi). 3. GF0 then permits fine gain adjustment to 1 Vpp. The total gain is accrued from GR0 x GF0.
GR0 Code 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 Adr 0x11, bit 2:0 Range RIN0 = 0x9 0.5 1.0 1.3 1.7 2.2 2.6 3.3 4.0 OF0 Code 0x00 0x01 ... 0x1F
Offset Calibration CH0 To calibrate the offset the reference source must first be selected using VOS0 (see Offset Calibration CH1 and CH2 for further information). For the CH0 path the dependent source VDC is identical to source VDC1.
VOS0 Code 0x0 0x1 0x2 0x3 Adr 0x13, bit 5:4 Source 0.05 * V(ACO) 0.5 V 0.25 V VDC (i.e. VDC1)
Table 35: Offset Reference Source CH0
OR0 Code 0x0 0x1 0x2 0x3 Adr 0x12, bit 1:0 Range x1 x2 x6 x12
Table 36: Offset Range CH0
Adr 0x12, bit 7:2 Factor 0 0.0322 0.0322 * OF0 1
Range RIN0 = 0x9 2.0 4.1 5.3 6.7 8.7 10.5 13.2 16.0
Code 0x20 0x21 ... 0x3F
Factor 0 -0.0322 -0.0322 * OF0 -1
Table 37: Offset Factor CH0
Table 33: Gain Range CH0
GF0 Code 0x00 0x01 ... 0x1F Adr 0x11, bit 7:3 Factor 1.00 1.06 6.25 6.25
GF 0 31
Table 34: Fine Gain Factor CH0
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 25/39 SIGNAL LEVEL CONTROL and SIGNAL MONITORING Via the controlled sensor current source (pin ACO) iCMQ can keep the input signals for the internal sineto-digital converter constant regardless of temperature and aging effects by tracking the sensor supply. Both the controller operating range and input signal amplitude for the controller are monitored and can be enabled for error messaging. A constant current source can be selected for the ACO output when setting the signal conditioning; the current range for the highside current source is adjusted using ADJ(6:5).
ADJ (4:0) Code 0x00 0x01 ... 0x19 ... 0x1F Adr 0x10, bit 3:0; Adr 0x0F, bit 7 Square control ADJ(8:7) = 00 Vpp() ca. 300 mV (60 %) Vpp() ca. 305 mV (61 %)
77 Vpp() 300 mV 77-(1.25Code)
Vpp() ca. 500 mV (98 %) ... Vpp() ca. 600 mV (120 %)
Table 40: Internal Sin/Cos Signal Amplitude For Square Control In operation with the active square control mode ADJ(4:0) sets the internal signal amplitudes according to the relation (PCH1-NCH1) + (PCH2-NCH2); these should be set to 0.25 Vpk.
ADJ (4:0) Code 0x00 0x01 ... Adr 0x10, bit 3:0; Adr 0x0F, bit 7 Sum control ADJ(8:7) = 01 VDC1 + VDC2 ca. 245 mV VDC1 + VDC2 ca. 249 mV
77 VDC1 + VDC2 245mV 77-(1.25Code)
Figure 5: Internal signal level monitoring and test signals in Calibration 2 mode (example for ADJ(8:0) = 0x19; see Elec. Char. Nos. 605 and 606 regarding Vt()min and Vt()max).
ADJ (8:7) Code 00 01 10 11 Adr 0x10, bit 7:6 Function Sine/cosine square control Sum control Constant current source Not permitted (device test only)
0x1F
VDC1 + VDC2 ca. 490 mV
Table 41: DC Setpoint For Sum Control
ADJ (4:0) Code 0x00 0x01 ... 0x1F Adr 0x10, bit 3:0; Adr 0x0F, bit 7 Constant current source ADJ(8:7) = 10 I(ACO) ca. 3.125% Isc(ACO) I(ACO) ca. 6.25% Isc(ACO) I(ACO) 3.125% (Code + 1) Isc(ACO) I(ACO) ca. 100% Isc(ACO) See Elec. Char. No. 602 for Isc(ACO)
Table 38: Controller Operating Modes
ADJ (6:5) Code 00 01 10 11 Adr 0x10, bit 5:4 Function 5 mA - Range 10 mA - Range 25 mA - Range 50 mA - Range
Notes
Table 42: I(ACO) With Constant Current Source
Table 39: ACO Output Current Range (applies for control modes and constant current source)
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 26/39 SINE-TO-DIGITAL CONVERSION
SELRES Value Adr 0x1C, bit 6:0; Adr 0x1B, bit 7:0 STEP IPF fin()max Angle Steps Interpolation Permissible Input Per Period Factor Frequency (MTD=0x8) 4 8 12 16 20 24 32 40 48 64 80 96 100 128 192 200 384 400 1 2 3 4 5 6 8 10 12 16 20 24 25 32 48 50 96 100 500 kHz 500 kHz 200 kHz 200 kHz 200 kHz 166 kHz 125 kHz 100 kHz 83 kHz 62.5 kHz 50 kHz 40 kHz 40 kHz 30 kHz 20 kHz 20 kHz 10 kHz 10 kHz
0x00E0 0x01B0 0x02A0 0x0398 0x0414 0x0590 0x078C 0x090A 0x0B88 0x0F86 0x1305 0x1784 0x1804 0x1F83 0x2F82 0x3102 0x5F81 0x6301
iC-MQ's converter resolution can be set using SELRES. For a resolution of 4, four angle steps per input signal period are generated so that the switching frequency at the A and B output matches the sine frequency at the input. The programmable converter hysteresis is determined by SELHYS. It is set in multiples of the increment size and may have a maximum of 45 of the input signal period.
SELHYS Code 0x0 0x1 0x2 0x3-0xD 0xE 0xF* Notes Adr 0x1D, bit 3:0 Function Nearly no hysteresis 1 increment ( 0.9) 2 increments ( 1.8) 3-13 increments ( 2.7-11.7) SELRES(6:1) increments (0.5 LSB) SELRES(6:0) increments *) Not permissible with SELRES = 0x00E0
Table 44: Converter Hysteresis
Table 43: Converter Resolution
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 27/39 OUTPUT SETTINGS AND ZERO SIGNAL The set interpolation factor IPF determines the number of A/B signal cycles generated internally which are counted via register POS to enable the positioning of the zero pulse. At a sine/cosine phase angle of zero degree the A/B cycle count starts at POS = 0, and the highest cycle count is reached when POSmax = IPF-1. The internal A/B signal cycle adheres to the following pattern: A1100 B1001 Table 45: Internal A/B Signal Cycle Inversions and reversals can be selected for the output of the A/B/Z signals and any logic combination for the output of the zero signal. The output logic pairs parameters CFGABZ in accordance with the table below:
CFGABZ Bit 7 6 5 4 Adr 0x19, bit 7:0 Function and Description Output inversion for channel A: PA<>NA PA = P1i xor CFGABZ(7) Output inversion for channel B: PB<>NB PB = P2i xor CFGABZ(6) Output inversion for index channel: PZ<>NZ PZ = P0i xor CFGABZ(5) Exchange of A/B signal assignation 0: P1i = A, P2i = B 1: P1i = B, P2i = A Zero Signal Logic CFGABZ(3:0) 3 2 1 0 Enable for A = 1, B = 1 Enable for A = 1, B = 0 Enable for A = 0, B = 0 Enable for A = 0, B = 1
Zero Signal Generation The generation of the zero signal is dependant on the internal enable signal ZIn which is produced by comparing the processed X1 and X2 input signals. The offset calibration of CH0 influences the width of the enable signal so that the correct position of ZIn should be checked before the zero signal logic is configured. In Mode ABZ this is possible at the error signal output (pin ERR; required settings are EMASKA = 0x010 and EMTD = 0x0).
Figure 7: Signal path from ZIn to PZ/NZ The positioning of the zero signal by CFGZPOS is relative to the internal A/B cycle count POS. A cycle must be selected across which enable signal ZIn is centered as far as is possible. For cycle counts which cannot be achieved due to a smaller interpolation factor no zero signal is generated.
CFGZPOS Bit 7 (6:0) Adr 0x1A, bit 7:0 Description Mask Enable (zero signal position determined by POS) POS = A/B cycle count nl (releases zero signal output)
Table 46: Output Logic
Table 47: Zero Signal Positioning
ENZFF Bit 0 1 Adr 0x02, bit 4 Description Zero signal output with state change of P0i Zero signal output synchronized with A/B signal
Table 48: Zero Signal Synchronization
Figure 6: Signal Path from A and B to PA/NA and PB/NB
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 28/39 Description Of CFGABZ Setup
Figure 9: Function of CFGABZ(4)
Figure 10: Function of CFGABZ(7)
Figure 8: Function of zero signal logic CFGABZ(3:0) (Example for CFGZPOS(7)=1, CFGZPOS(6:0)=0x6) Setup Example 1 Incremental ABZ output with a zero signal of 180 synchronous with the A signal at PA: CFGABZ = "0000 1100" Setup Example 2 Incremental ABZ output with a zero signal of 270 which can be synchronized externally with a 90 zero pulse for PA = 1 und PB = 1: CFGABZ = "1100 0111"
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 29/39 Output Driver Configuration The output drivers can be used as push-pull, lowside or highside drivers; the mode of operation is determined by TRIHL(1:0). In order to avoid steep edges when transmitting via short wires the slew rate can be set using SSR to suit the length of the cable. This can result in a limiting of the maximum permissible output frequency if at the same time the RS422 specification is to be adhered to (for example, to 300 kHz at a slew rate of 300 ns; the tolerances in Electrical Characteristics, numbers 506/507, must be observed). The driver output short-circuit current can be set by SIK and can be minimized when connecting to logic or to an external 24 V line driver. If the outputs are used as RS422-compatible 5 V drivers, it is recommended that SIK = 11 to keep the power dissipation of iC-MQ low.
TRIHL Code 00 01 10 11 Adr 0x1E, bit 1:0 Function Push-pull operation Highside driver mode (P channel open drain) Lowside driver mode (N channel open drain) Not permitted SIK Code 00 01 10 11 Note Adr 0x1E, bit 5:4 Function typ. typ. typ. typ. 2 mA, linking logic or driver ICs 8 mA 40 mA 100 mA, recommended for RS422
See Elec. Char. Nos. 503/504
Table 51: Output Short-Circuit Current Minimum Phase Distance The minimum phase distance for A/B/Z and CPD/CPU/CP output signals can be preselected using MTD(3:0). This setting limits the maximum possible output frequency for safe transmission to counters which cannot debounce spikes or only permit a low input frequency. When preselecting the minimum edge distance the configuration of the RS422 output drivers (with regard to the driver current and slew rate) and the length of cable used must be taken into account.
MTD Code 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF Note Adr 0x1D, bit 7:4 Mode ABZ : tMTD 220 ns 410 ns 600 ns 800 ns 1.0 s 1.2 s 1.4 s 1.6 s 220 ns 410 ns 600 ns 800 ns 1.0 s 1.2 s 1.4 s 1.6 s
Mode 191/193: tclk()lo 110 ns 205 ns 300 ns 400 ns 500 ns 600 ns 700 ns 800 ns 50 ns 50 ns 50 ns 50 ns 50 ns 50 ns 50 ns 50 ns
Table 49: Output Drive Mode
SSR Code 00 01 10 11 Note Adr 0x1E, bit 3:2 Function Nominal value 12 ns Nominal value 25 ns Nominal value 80 ns Nominal value 220 ns See Elec. Char. Nos. 506/507
Table 50: Output Slew Rate
All timing specifications are nominal values, see Elec. Char. No. 515 for tolerances.
Table 52: Minimum Phase Distance
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 30/39 ERROR MONITORING AND ALARM OUTPUT iC-MQ monitors the input signals, the internal interpolator and the sensor supply controller via which the input signal levels are stabilized. If the sensor supply tracking unit reaches its control limits this can be interpreted as an end-of-life message, for example. Three separate error masks stipulate whether error events are signaled as an alarm via the current-limited open drain I/O pin ERR (mask EMASKA), whether they cause the RS422 line drivers to shutdown or not (mask EMASKO) or whether they are stored in the EEPROM (mask EMASKE). The display logic (via EPH) and the minimum alarm indication time (via EMTD) can be set for I/O pin ERR; an internal pull-up current source can be switched in via EPU. ERR pin also has an input function for switching iC-MQ to test mode (see page 33) and for the acceptance of a system error message in normal operation (only for EPH = 0).
EPH Code 0 1 Adr 0x15, bit 2 Pin Logic Low on error (otherwise Z) Z on error (otherwise low) EMASKA Bit 9 8 7 6 Adr 0x15, bit 1:0; Adr 0x14, bit 7:0 Error event Line count error (wrong count of sine periods between two zero pulses) Temporal tracking error (out-of-sync: position output differs from actual angle, e.g. after cycling power) Loss of tracking (excessive input frequency) Configuration error* (SDA or SCL pin error, no acknowledge signal from EEPROM or invalid check sum) Excessive temperature warning Ungated index enable signal ZIn (comparated X1/X2 inputs for CFGABZ and CFGZPOS adjustment) Control error 2: range at max. limit Control error 1: range at min. limit Signal error 2: clipping due to excessive input level Signal error 1: loss of signal (poor input level or s/c phase out of range) Function Enable: event will be displayed Disable: event will not be displayed *) The line drivers remain high impedance (tristate) when cycling power.
5 4
3 2 1 0 Code 1 0 Notes
Table 57: Error Event Mask for Alarm Output
EMASKO Bit 9 Adr 0x17, bit 1:0; Adr 0x16, bit 7:0 Error event Line count error (wrong count of sine periods between two zero pulses) Temporal tracking error (out-of-sync: position output differs from actual angle, e.g. after cycling power) Loss of tracking (excessive input frequency) Configuration error* (ROM bit with fixed value = 1) SDA or SCL pin error, no acknowledge signal from EEPROM or invalid check sum Excessive temperature warning System error: I/O pin ERR pulled to low by an external error signal (only permitted with EPH = 0) Control error 2: range at max. limit Control error 1: range at min. limit Signal error 2: clipping due to excessive input level Signal error 1: loss of signal (poor input level or s/c phase out of range) Function Enable: event triggers tri-state Disable: event does not cause tri-state *) The line drivers remain high impedance (tristate) when cycling power.
Table 53: Alarm Input/Output Logic
EMTD Code 0x0 0x1 0x2 0x3 Adr 0x15, bit 5:3 Indication Time 0 ms 12.5 ms 25 ms 37.5 ms
Code 0x4 0x5 0x6 0x7
Indication Time 50 ms 62.5 ms 75 ms 87.5 ms
8 7 6
Table 54: Minimum Alarm Indication Time
EPU Code 0 1 Adr 0x17, bit 2 Function No internal pull-up active Internal 300 A pull-up current source active
5 4 3 2 1 0 Code 1 0 Notes
Table 55: Pull-Up Enable for Alarm Output ERR
PDMODE Code 0 1 Adr 0x18, bit 6 Function Line driver active when no error persists Line driver active only after cycling power
Table 58: Error Event Mask for Driver Shutdown
Table 56: Driver Activation
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 31/39 Error Protocol Out of the errors enabled by EMASKE both the first (under ERR1) and last error (under ERR2) which occur after the iC-MQ is turned on are stored in the EEPROM. The EEPROM also has a memory area in which all occurring errors can be stored (ERR3). Only the fact that an error has occurred can be recorded, with no information as to the time and count of appearance of that error given. Error recording can be used to statistically evaluate the causes of system failure, for example.
EMASKE Bit 9 8 7 6 5 4 3 2 1 0 Code 1 0 Adr 0x18, bit 5:0; Adr 0x17, bit 7:4 Error event Line count error (wrong count of sine periods between two zero pulses) -- Loss of tracking (excessive input frequency) -- Excessive temperature warning System error: I/O pin ERR reads low by an external error signal (only permitted with EPH = 0) Control error 2: range at max. limit Control error 1: range at min. limit Signal error 2: clipping due to excessive input level Signal error 1: loss of signal (poor input level or s/c phase out of range) Function Enable: event will be latched Disable: event will not be latched
Line Count Error The line count error feature is particularly interesting for encoder systems. The disc is checked anew with each zero pulse, with the number of sine cycles counted until the next zero pulse occurs. If the direction of rotation is changed, the check is aborted. The line count is then stored under LINECNT minus 1, i.e. for a code disc with 256 lines LINECNT records a value of 255. If the counted line number does not match the number already stored in LINECNT, a line count error is set. In mode System Test signal TP1 indicates when the line count check is first ended. Temperature Monitoring If the temperature warning threshold is exceeded an excessive temperature message is generated which is processed in the temperature monitor block (Tw corresponds to T2 ). Exceeding the temperature warning threshold can be signaled at pin ERR or used to shut down the line drivers (via mask EMASKO). The temperature warning is deleted when the temperature drops below Tw -Thys . If the temperature shutdown threshold Toff = Tw + T is exceeded the line drivers are shut down independent of EMASKO.
Table 59: Error Event Mask for EEPROM Savings
ERR1 ERR2 ERR3 Bit 6:0 Code 0 1 Adr 0x31, bit 1:0; Adr 0x30, bit 7:0 Adr 0x32, bit 3:0; Adr 0x31, bit 7:2 Adr 0x33, bit 5:0; Adr 0x32, bit 7:4 Error Event Assignation according to EMASKE Function No event Registered error event
Table 60: Error Protocol
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 32/39 REVERSE POLARITY PROTECTION iC-MQ is protected against a reversal of the supply voltage and has short-circuit-proof, error-tolerant line drivers. A defective device cable or one wrongly connected is tolerated by iC-MQ. All circuitry components which draw the monitored supply voltage from VDDS and GNDS are also protected. The following pins are also reverse polarity protected: PA, NA, PB, NB, PZ, NZ, ERR, VDD, GND and ACO. Conditions: This is based on the condition that GNDS only receives load currents from VDDS. The maximum voltage difference between GNDS and another pin should not exceed 6 V, the exception here being pin ERR (see Test Mode page 33).
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 33/39 TEST MODE iC-MQ switches to test mode when a voltage greater than VTMon is applied to pin ERR (precondition: EMODE(0) = 1). In response iC-MQ transmits its setup settings as current-modulated data using error signal I/O pin ERR either directly from the RAM (for EMODE2 = 1) or after re-reading the EEPROM (for EMODE2 = 0). Should the voltage at the ERR pin fall below VTMoff test mode is terminated and data transmission aborted. The clock rate for the data output is determined by ENFAST. Two clock rates can be selected: 780 ns for ENFAST = 1 or 3.125 s for ENFAST = 0 (see Electrical Characteristics, B12, for clock frequency and tolerances). Data is output in Manchester code via two clock pulses per bit. To this end the lowside current source switches between a Z state (OFF = 0 mA) and an L state (ON = 2 mA). The bit information lies in the direction of the current source switch: Zero bit: change of state Z L (OFF to ON) One bit: Change of state L Z (ON to OFF)
EMODE Code 00 01 10 11 Adr 0x15, bit 7:6 Function during test mode Normal operation Transmission of error and OEM data* Normal operation Transmission of EEPROM contents (0x0-0x7F)
Function following test mode Normal operation Repeated read out of EEPROM Repeated read out of EEPROM Repeated read out of EEPROM
Notes
*) Selectable address ranges: EMODE2 = 0: EEPROM addresses 0x24 to 0x7F EMODE2 = 1: RAM addresses 0x3B to 0x43
Table 61: Test Mode
EMODE2 Code 0 Adr 0x18, bit 7 Register selection Reading/sending external configuration data (DEVID is device address) Sending internal configuration data (ENSL = 1)
Address range for EMODE = 01 EEPROM address range 0x24-0x7F
1
RAM address range 0x3B-0x43
Transmission consists of a start bit (a one bit), 8 data bits and a pause interval in Z state (the timing is identical with an EEPROM access via the I2 C interface). Example: byte value = 1000 1010 Transmission including the start bit: 1 1000 1010 In Manchester code: LZ LZZL ZLZL LZZL LZZL
Table 62: Register And Address Selection For Test Mode
VP VP C21 100nF 7 VP C22 U22-S 100nF AD8029 VN 4 8 VP U23-S LM393 GND 4 VP 6 5 U23-B LM393
+
7
ERR
JP4 M22 IRLML6401 R26 100k R28 51k
R24 470 VP C24 100pF R23 2K D21 LL4148 2 3 8 5 R22 365k 4 VDD C23 100nF
dra_mq1d_error_schem
max. 5V VDD
U22-A
Decoding of the data stream: ZZZZZZ LZ LZ ZL ZL ZL LZ ZL LZ ZL ZZZZZZ Pause 1 1 0 0 0 1 0 1 0 Pause
DATA_ON
M21 2N7002 R21 475k
-
U23-A LM393 6 2 3
+ NDIS
8 VP
AD8029
+
R25 2k 1
C26 100nF
DATA_OUT
R27 100k
U21 LM285
C25 100nF
Figure 11: Example circuit for the decoding and conversion of the current-modulated signals to logic levels.
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 34/39 Quick programming in the single master system For the purpose of signal conditioning it is possible to reprogram iC-MQ quickly. If test mode is quit and EMODE = 00, iC-MQ reads the configuration data in again. In place of the standard EEPROM (DEVID 0x50) an EEPROM with a different device address can be read in which can be stored under DEVID (address 0x00, bit 6:0). In operating modes Mode ABZ, System Test and Mode 191/193 the content of the EEPROM is read in its entirety. For other modes the address area is limited to 0x0-0x31 so that the configuration time for either calibration or IC testing is shortened. If the setup is switched to test mode during the readin procedure, readin is aborted and only repeated once test mode has been terminated. Quick programming in the multimaster system Fast programming of iC-MQ, byte for byte, is possible with a multimaster-competent programming device. To this end the integrated I2 C slave mode must be enabled by ENSL; iC-MQ then reacts to the device ID 0x55.
If no EEPROM is connected, iC-MQ automatically sets the I2 C slave mode enable (after a maximum of 150 ms, see Electrical Characteristics, D11) and deactivates the digital section (ENSL = 1 and END = 0 are set). Any number of bytes can be written at any one time; the received data is accepted directly into the RAM register. The conditions given in the following table must be taken into consideration here. After programming END = 1 must be set to restart sine-to-digital conversion in the selected mode of operation.
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 35/39 EXAMPLE APPLICATIONS Figure 12 is a circuit diagram of an optical encoder with an incremental output of quadrature signals as RS422compatible differential signals which can be terminated by 100 at the controller end. By way of an alternative the magnetic encoder in Figure 13 uses magnetoresistive sensor bridges. An external overvoltage protection circuit may be realized employing TVS diodes plus a PolyFuse in the VDD line, for instance.
Disc iC-LSHB
iC-MQ
Figure 12: Example application with an optical encoder
iC-MQ
Figure 13: Example application with a magnetic encoder
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 36/39 When iC-MQ is used in 24 V systems, with supply voltages of 5 V to 30 V for example, it can be combined with iC-DL which acts as a line driver with an integrated line adaptation feature (Figure 14). A reduced driving capability of iC-MQ is sufficient (SIK = 00) to operate iC-DL so that the current required is reduced at the 5 V end. If an LDO voltage regulator is selected, the circuit is suitable for a supply range of 4.5 V to 30 V without any changes having to be made. The wiring of the iC-DL error message output (pin NER) to the PLC is not necessary if the iC-MQ error mask is set for output shutdown (EMASKO). In the event of error the pull-down current sources ensure that a low signal is produced at the iC-DL inputs on all lines which the controller recognizes as an error. If there is an overload at the outputs, via its temperature protection unit iC-DL itself makes sure that the driver outputs are shutdown (tristate) - which the controller also classes as an error. In addition iC-MQ can transmit the overload to the error memory as a system error when information is returned to the bidirectional I/O pin ERR (as shown).
iC-MQ iC-DL
Figure 14: Example application with a 24 V line driver
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 37/39 APPLICATION HINTS In-circuit programming of the EEPROM Access to the EEPROM is unhindered when the iCMQ supply voltage is kept below power down reset threshold VDDoff. In this case an EEPROM which operates at a supply voltage of 2.5 V and above is required. If 3.3 V are necessary to power the EEPROM, iC-MQ's supply voltage can be raised at a maximum to power on threshold VDDon; this must occur without overshooting. The supply voltage provided by pins VDDS and GNDS can be used to power the EEPROM; shutdown only occurs with reverse polarity. Here, the load-dependent voltage drop at both switches must be taken into account; see Vs(VDDS) and Vs(GNDS) in the Electrical Characteristics, C01 and C02. Absolute angle accuracy and edge jitter The precise setting of the signal conditioning unit for correction of the analog input signals is crucial to the result of interpolation; the absolute angle error obtained determines the minimum signal jitter. Here, the effect on the transition distance of the A/B output signals is not always the same but instead dependent on the absolute phase angle of the input signals. The following gives an example for an interpolation factor of 100, i.e. 400 edges per sine period. The offset error in the cosine signal has the strongest effect on the absolute angle error at 90 and 270; at 0 and 180 its influence on the transition distance is the most marked. With a range setting of OR1 = OR2 = 00 and VOSSC = 01 the offset error can be compensated for by an increment of 3.9 mV. If the offset has been compensated for incorrectly by one step (1 LSB), the absolute angle error would increase by ca. 0.45 and the transition distance vary by approximately +/- 0.8 %. Similar conditions apply to the sine signal, with the sole difference that the maxima would be shifted by 90. An error in amplitude has the strongest effect on the absolute angle error at 45, 135, 225 and 315; the biggest change in the transition distance can be observed at 0, 90, 180 and 270. iC-MQ can compensate for the amplitude ratio in steps of 1.5 % so that incorrect compensation by 1 LSB would increase the absolute angle error by ca. 0.42. The transition distance would then vary by +/- 1.5 %. A phase error between the sine and cosine signals (a deviation in phase shift from the ideal 90) has the most marked influence on the absolute angle error at 0, 90, 180 and 270. The greatest effect on the transition distance is noted at 45, 135, 225 and 315. iC-MQ's phase correction feature permits a step size of 0.64 so that incorrect compensation by 1 LSB would increase the absolute angle error by ca. 0.64. The transition distance would then vary by +/- 1.1 %. In a perfect signal conditioning procedure it can be assumed that the residual error constitutes half a compensation step respectively. With this, in theory iCMQ would achieve an absolute angle accuracy of ca. 0.5, with the transition distance varying by ca. +/1.5 %. The linearity error of the interpolator must also be taken into consideration; this increases the absolute angle error by ca. 0.12 and the variation in transition distance by 0.4 %. With ideal, almost static input signals iC-MQ then obtains an absolute angle accuracy of 0.62 and a variation in transition distance of under 2 %. Information on the demo board The default delivery status of demo board EVAL MQ1D is such that it expects differential sine/cosine signals at inputs X3 to X6 with an amplitude of 125 mV, i.e.
V (X 4) = 2.5 V + 0.125 Vsin(t) V (X 3) = 2.5 V - 0.125 Vsin(t) V (X 5) = 2.5 V + 0.125 Vsin(90 + t) V (X 6) = 2.5 V - 0.125 Vsin(90 + t) Outputs PA, NA, PB and NB generate a differential A/B signal with an angle resolution of 4 (an interpolation factor of 1). When high sine input frequencies are applied or the resolution is increased, the minimum phase distance (MTD), short-circuit current limit (SIK) and driver slew rate (SSR) must be adjusted to meet requirements. For example, a minimum phase distance of MTD = 8 should be selected with a resolution of 200 (an interpolation factor of 50) when input frequencies of up to 20 kHz are to be applied.
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 38/39
iC-Haus expressly reserves the right to change its products and/or specifications. An info letter gives details as to any amendments and additions made to the relevant current specifications on our internet website www.ichaus.de/infoletter; this letter is generated automatically and shall be sent to registered users by email. Copying - even as an excerpt - is only permitted with iC-Haus' approval in writing and precise reference to source. iC-Haus does not warrant the accuracy, completeness or timeliness of the specification and does not assume liability for any errors or omissions in these materials. The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, fitness for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and no guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of the product. iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product. As a general rule our developments, IPs, principle circuitry and range of Integrated Circuits are suitable and specifically designed for appropriate use in technical applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. In principle the range of use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued annually by the Bureau of Statistics in Wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in Hanover (Hannover-Messe). We understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations of patent law. Our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can be put to.
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 39/39 ORDERING INFORMATION
Type iC-MQ Evaluation Board iC-MQ
Package TSSOP20
Order Designation iC-MQ TSSOP20 iC-MQ EVAL MQ1D
For technical support, information about prices and terms of delivery please contact: iC-Haus GmbH Am Kuemmerling 18 D-55294 Bodenheim GERMANY Tel.: +49 (61 35) 92 92-0 Fax: +49 (61 35) 92 92-192 Web: http://www.ichaus.com E-Mail: sales@ichaus.com
Appointed local distributors: http://www.ichaus.com/sales_partners

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